3. Improving Productivity with IP Blocks

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Skills You'll Learn

Primality Test, Verilog, Digital Design, Static Timing Analysis

Reviews

4.6 (1,174 ratings)

  • 5 stars
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    20.10%
  • 3 stars
    4.77%
  • 2 stars
    1.44%
  • 1 star
    1.87%

KS

Jul 30, 2020

This is an extremely good course and I learned a lot. Thank you very much sir "Timothy Scherr " and all the people who make this a such a nice one. Also thank you very much "COURSERA" !!!

RD

Oct 24, 2018

Very good course, focused on the quartus prime tool and touch a lot of topics on FPGA design, optimization, time analysis and a little of comparison between Altera and other FPGA vendors.

From the lesson

Programmable logic design using schematic entry design tools

Taught By

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    Timothy Scherr

    Senior Instructor and Professor of Engineering Practice

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