Back to VLSI CAD Part II: Layout
University of Illinois Urbana-Champaign

VLSI CAD Part II: Layout

You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class).

Status: Network Routing
Status: Algorithms
IntermediateCourse24 hours

Featured reviews

SM

5.0Reviewed Jun 18, 2020

Great great great course. Highly recommended for people interested in VLSI CAD design.

GS

5.0Reviewed Apr 23, 2020

Nicely explained and well structured course and the best part of the course is the way of teaching and assignment ..Keep learning and keep growing..

DS

5.0Reviewed Sep 22, 2019

An awesome course which I can put to great use in my academic life.

SM

5.0Reviewed Jun 26, 2023

Excellent course to understand the concepts of Placement, Mapping, Routing and Static Timing Analysis

MM

5.0Reviewed May 13, 2020

It was a great course, I learned a lot of new things from it. And the presentation and explanation of concepts by Prof. Rob A. Rutenbar were amazing!!!

NN

5.0Reviewed Aug 20, 2022

this course was assum thanking you coursera for given this wondarful opportinuty.

SK

5.0Reviewed Jul 13, 2021

Very well curated course! It is exhaustive in terms of the invigorating assignments and the lucid explanations help satiate the curiosity about the journey from Logic->Layout in VLSI.

ST

5.0Reviewed Jun 21, 2020

Excellent ; every on who's specialisation is VLSI has to do this course;

KJ

5.0Reviewed Jul 29, 2019

Good course content and prof. `s teaching method makes it easy to comprehend quite quickly.

GA

5.0Reviewed Oct 31, 2022

thanks Coursera,for given me a wonderful opportinituty it was very help me to completion of my VLSI Mtech thanks & Regards,Arla Girisubash

AL

5.0Reviewed Oct 20, 2018

Great basic overview of the core design principles for EDA

AT

5.0Reviewed Jun 13, 2020

It delivers what it promises in a structured and concise manner which makes the whole experience fast and effective.

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