Hardware Description Languages for FPGA Design

Hardware Description Languages for FPGA Design

This course is part of FPGA Design for Embedded Systems Specialization

Instructors: Timothy Scherr

What you'll learn

Explain the role of HDLs in design entry and verification for FPGAs and ASICs
Utilize HDL software tools for FPGA development

Skills you'll gain

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Assessments

1 quiz, 5 assignments

Taught in English

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This course is part of the FPGA Design for Embedded Systems Specialization

When you enroll in this course, you'll also be enrolled in this Specialization.

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There are 4 modules in this course

This course can also be taken for academic credit as ECEA 5361, part of CU Boulder’s Master of Science in Electrical Engineering degree.

Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.

This module introduces the basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.

What's included

10 videos3 readings2 assignments4 programming assignments1 discussion prompt

10 videosTotal 48 minutes

Introduction to Hardware Description Languages for FPGA Design4 minutesPreview module
Why Learn VHDL?1 minute
FPGA Design Flow3 minutes
Intro to VHDL: Finite State Machine3 minutes
How to speak VHDL, first phrases6 minutes
VHDL Assignments, Operators, Types3 minutes
VHDL Rules and Syntax, Interface Ports3 minutes
VHDL in ModelSim: Download and Install3 minutes
VHDL in ModelSim: Adding to your Toolkit6 minutes
Submitting VHDL Programming Assignments11 minutes

3 readingsTotal 140 minutes

Hardware Description Languages for FPGA Design Assessment Strategy10 minutes
Misson 2-001: Week 1 Readings120 minutes
Files for Week 1 Programming Assignments10 minutes

2 assignmentsTotal 60 minutes

VHDL Find the Code Errors30 minutes
Module 1 Quiz30 minutes

4 programming assignmentsTotal 240 minutes

VHDL 2-bit Comparator60 minutes
VHDL Correct Errors60 minutes
VHDL Majority Vote60 minutes
VHDL 1-bit Full Adder60 minutes

1 discussion promptTotal 10 minutes

Introduce Yourself10 minutes

In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.

What's included

10 videos2 readings1 assignment5 programming assignments

10 videosTotal 52 minutes

Learning to speak VHDL (Intro)1 minutePreview module
Combinatorial Circuits4 minutes
Synchronous Logic: Latches and Flip Flops4 minutes
Synchronous Logic: Counters and Registers6 minutes
Buses and Tristate Buffers3 minutes
Modular Designs: Components, Generate and Loops in VHDL3 minutes
Test Benches in VHDL: Combinatorial8 minutes
Test Benches in VHDL: Synchronous5 minutes
Memory in VHDL7 minutes
Finite State Machines in VHDL8 minutes

2 readingsTotal 130 minutes

Week 2 Readings120 minutes
Files for Week 2 Programming Assignments10 minutes

1 assignmentTotal 30 minutes

Module 2 Quiz30 minutes

5 programming assignmentsTotal 480 minutes

VHDL 74LS163 Binary Counter120 minutes
VHDL Make a Memory60 minutes
VHDL Finite State Machine60 minutes
VHDL ALU120 minutes
VHDL FIFO120 minutes

This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.

What's included

9 videos2 readings1 quiz1 assignment4 programming assignments

9 videosTotal 92 minutes

Verilog for fun and profit (intro)3 minutesPreview module
Your First Verilog phrase11 minutes
Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing12 minutes
Verilog Statements and Operators16 minutes
Verilog Modules, Port Modes and Data Types10 minutes
Verilog Structure10 minutes
Testing with ModelSim5 minutes
Verilog Evaluation11 minutes
Submitting Verilog Programming Assignments10 minutes

2 readingsTotal 80 minutes

Week 3 Readings70 minutes
Files for Week 3 Programming Assignments10 minutes

1 quizTotal 20 minutes

Verilog Find the Errors20 minutes

1 assignmentTotal 30 minutes

Module 3 Quiz30 minutes

4 programming assignmentsTotal 180 minutes

Verilog 2-bit Comparator30 minutes
Verilog Correct Errors60 minutes
Verilog Majority Vote30 minutes
Verilog 4-bit Full Adder60 minutes

In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.