SystemVerilog Tutorials: Hardware Design & Verification
Completed by Abed Yosef
October 8, 2026
5 hours (approximately)
Abed Yosef's account is verified. Coursera certifies their successful completion of SystemVerilog Tutorials: Hardware Design & Verification
What you will learn
Design synthesizable SystemVerilog modules and integrate combinational and sequential logic to form complete digital subsystems.
Implement an Arithmetic Logic Unit (ALU) capable of performing core operations and basic arithmetic for calculator functionality.
Develop a finite state machine (FSM) to control complex system modes (calculator modes), user inputs, and operation sequencing.
Simulate, verify, and debug SystemVerilog designs to ensure functionality of the full calculator system.
Skills you will gain
- Category: Hardware Design
- Category: Data Synthesis
- Category: Code Reusability
- Category: Analysis
- Category: Process Optimization
- Category: Simulation and Simulation Software
- Category: Design
- Category: Field-Programmable Gate Array (FPGA)
- Category: Data Structures
- Category: Application Specific Integrated Circuits
- Category: Verification And Validation
