The Programming Assignments need to be more elaborate, things like reset is active low or active high and more details should be mentioned.

The course is good. It will enhance your vhdl and verilog skills but there are some places where i found insufficient details.

FIFO assignments in both Verilog and VHDL should define purpose of all the internal nets and registers listed in the problem.

Siento que faltan mas ejemplos y practicas, y en cuanto al apartado de lenguaje Verilog falta explicar aun mas sintaxis

The lecturers explain the concepts very well, but there are some things that are just assumed to be easily understood.

Teaching methodology requires a lot more improvement. Assignments are challenging and its nice to try.

this course is given good idea of Hardware Description Language and i understood the concepts well.

Course content is moderate. But also have complexity level higher for a beginner.

its a very nice course. Its help me a lot to understand the basic of fpga.

A very engaging course to do for beginners having fundamentals strong.

Explanations are not that good for some circuits like memory

There should have been more examples of problems.

Good course, but some exercises need corrections

a big thank you to all the professiors

Concise, practical and useful

It should be more elaborative

Valuable and Informative

cours très intéressant

i love this course

BEST FOR THE BASIC

Good

good

The course is split into 2 weeks of VHDL and 2 weeks of Verilog, with two different instructors. Unfortunately, the first 2 weeks are really dragging down the quality of the course. They are riddled with bad explanations, omissions, and plain errors throughout. I'd go as far as to say the student learns the contents of those weeks because of the reading materials (which do a good job explaining what's actually going on), and despite the instructor video lectures , which are just leading the student astray.

The programming assignments in both parts of the course leave a lot to be desired with regard to the quality of specifications. They frequently don't explain how the list of control signals is supposed to interact, which signals are active high vs. active low, whether they are assumed to be synchronous or async etc.

I'm missing coverage of how exactly different subtle choices of writing the code affects the synthesis of the FPGAs in various ways, by way of examples that show what happens in those cases.

The course is OK, but the videos are terrible. The presenters do nothing more than just read the slides as they appear, which are sometimes just a page of code. In the VHDL section, I believe the presenter is seeing the material for the first time. I ended up just turning the audio off and treating the videos as a slide deck, which worked quite well. The assignments were fun.

Interesting course but exercises shall be reworked as sometimes it's not clear what is the expected output so we end up guessing via the testbench. Another issue is that some half backed quizzes prevent you from practicing the exercises until you pass even though practicing is key to understand the concepts...