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University of Illinois Urbana-Champaign
VLSI CAD Part II: Layout
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  2. Computer Science
  3. Algorithms
University of Illinois Urbana-Champaign

VLSI CAD Part II: Layout

Rob A. Rutenbar

Instructor: Rob A. Rutenbar

24,340 already enrolled

Included with Coursera Plus

•Learn more
6 modules
Gain insight into a topic and learn the fundamentals.
4.7

(282 reviews)

Intermediate level
Some related experience required
2 weeks to complete
at 10 hours a week
Flexible schedule
Learn at your own pace

6 modules
Gain insight into a topic and learn the fundamentals.
4.7

(282 reviews)

Intermediate level
Some related experience required
2 weeks to complete
at 10 hours a week
Flexible schedule
Learn at your own pace
  • About
  • Modules
  • Recommendations
  • Testimonials
  • Reviews

Skills you'll gain

  • Computer-Aided Design
  • Electronic Hardware
  • Electrical and Computer Engineering
  • Network Routing
  • Calculus
  • Algorithms
  • Data Structures
  • Hardware Design
  • Semiconductors
  • Application Specific Integrated Circuits
  • Computational Logic
  • Mathematical Modeling
  • Systems Design
  • Computer Architecture
  • Engineering Design Process

Details to know

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Assessments

7 assignments

Taught in English

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There are 6 modules in this course

You should complete the VLSI CAD Part I: Logic course before beginning this course.

A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class).

In this module you will become familiar with the course and our learning environment. The orientation will also help you obtain the technical skills required for the course.

What's included

2 videos2 readings1 assignment1 plugin

2 videos•Total 23 minutes
  • Welcome and Introduction•19 minutes•Preview module
  • Two Tools Tutorial•4 minutes
2 readings•Total 20 minutes
  • Syllabus•10 minutes
  • Tools For This Course•10 minutes
1 assignment•Total 5 minutes
  • Demographics Survey•5 minutes
1 plugin•Total 15 minutes
  • Welcome! Please tell us about yourself.•15 minutes

In this second part of our course, we will talk about geometry. We will begin with an overview of the ASIC layout process, and discuss the role of technology libraries, tech mapping (a topic we delay until the following week, to let those who want to do the Placer programming assignment have more time), and placement and routing. In this set of lectures, we focus on the placement process itself: you have a million gates from the result of synthesis and map, so, where do they go? This process is called “placement”, and we describe an iterative method, and a mathematical optimization method, that can each do very large placement tasks.

What's included

9 videos2 readings

9 videos•Total 163 minutes
  • Basics•17 minutes•Preview module
  • Wirelength Estimation•15 minutes
  • Simple Iterative Improvement Placement•12 minutes
  • Iterative Improvement with Hill Climbing•15 minutes
  • Simulated Annealing Placement•27 minutes
  • Analytical Placement: Quadratic Wirelength Model•14 minutes
  • Analytical Placement: Quadratic Placement•26 minutes
  • Analytical Placement: Recursive Partitioning•18 minutes
  • Analytical Placement: Recursive Partitioning Example•16 minutes
2 readings•Total 20 minutes
  • Week 1 Overview•10 minutes
  • Week 1 Assignments•10 minutes

Technology Mapping! We omitted one critical step between logic and layout, the process of translating the output of synthesis -- which is NOT real gates in your technology library -- into real logic gates. The Tech Mapper performs this important step, and it is a surprisingly elegant algorithm involving recursive covering of a tree. Another place where knowing some practical computer science comes to the rescue in VLSI CAD.

What's included

6 videos2 readings1 assignment1 programming assignment

6 videos•Total 102 minutes
  • Technology Mapping Basics•19 minutes•Preview module
  • Technology Mapping as Tree Covering•29 minutes
  • Technology Mapping—Tree-ifying the Netlist•13 minutes
  • Technology Mapping—Recursive Matching•9 minutes
  • Technology Mapping—Minimum Cost Covering•16 minutes
  • Technology Mapping—Detailed Covering Example•14 minutes
2 readings•Total 20 minutes
  • Week 2 Overview•10 minutes
  • Week 2 Assignments•10 minutes
1 assignment•Total 60 minutes
  • Problem Set #1•60 minutes
1 programming assignment•Total 180 minutes
  • Programming Assignment #3: Placer•180 minutes

Routing! You put a few million gates on the surface of the chip in some sensible way. What's next? Create the wires to connect them. We focus on Maze Routing, which is a classical and powerful technique with the virtue that one can "add" much sophisticated functionality on top of a rather simple core algorithm. This is also the topic for final (optional) programming assignment. Yes, if you choose, you get to route pieces of the industrial benchmarks we had you place in the placer software assignment.

What's included

9 videos2 readings1 assignment

9 videos•Total 144 minutes
  • Routing Basics•17 minutes•Preview module
  • Maze Routing: 2-Point Nets in 1 Layer•16 minutes
  • Maze Routing: Multi-Point Nets•12 minutes
  • Maze Routing: Multi-Layer Routing•12 minutes
  • Maze Routing: Non-Uniform Grid Costs•14 minutes
  • Implementation Mechanics: How Expansion Works•23 minutes
  • Implementation Mechanics: Data Structures & Constraints•18 minutes
  • Implementation Mechanics: Depth First Search•14 minutes
  • From Detailed Routing to Global Routing•15 minutes
2 readings•Total 20 minutes
  • Week 3 Overview•10 minutes
  • Week 3 Assignments•10 minutes
1 assignment•Total 60 minutes
  • Problem Set #2•60 minutes

You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design.

What's included

8 videos2 readings1 assignment1 programming assignment

8 videos•Total 148 minutes
  • Basics•7 minutes•Preview module
  • Logic-Level Timing: Basic Assumptions & Models•30 minutes
  • Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks•27 minutes
  • Logic-Level Timing: A Detailed Example and the Role of Slack•10 minutes
  • Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths•26 minutes
  • Interconnect Timing: Electrical Models of Wire Delay•16 minutes
  • Interconnect Timing: The Elmore Delay Model•14 minutes
  • Interconnect Timing: Elmore Delay Examples•14 minutes
2 readings•Total 20 minutes
  • Week 4 Overview•10 minutes
  • Week 4 Assignments•10 minutes
1 assignment•Total 60 minutes
  • Problem Set #3•60 minutes
1 programming assignment•Total 180 minutes
  • Programming Assignment #4: Router•180 minutes

There is no new content this week. Instead, you should focus on finishing the last problem set and completing the Final Exam.

What's included

3 assignments1 plugin

3 assignments•Total 185 minutes
  • End of Course Survey•5 minutes
  • Problem Set #4•60 minutes
  • Final Exam•120 minutes
1 plugin•Total 15 minutes
  • How was the course?•15 minutes

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Instructor

Instructor ratings

Instructor ratings

We asked all learners to give feedback on our instructors based on the quality of their teaching style.

4.4 (45 ratings)
Rob A. Rutenbar
Rob A. Rutenbar
2 Courses•66,197 learners

Offered by

University of Illinois Urbana-Champaign

Offered by

University of Illinois Urbana-Champaign

The University of Illinois at Urbana-Champaign is a world leader in research, teaching and public engagement, distinguished by the breadth of its programs, broad academic excellence, and internationally renowned faculty and alumni. Illinois serves the world by creating knowledge, preparing students for lives of impact, and finding solutions to critical societal needs.

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4.7

282 reviews

  • 5 stars

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  • 4 stars

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Showing 3 of 282

S
SM
5

Reviewed on Jun 18, 2020

Great great great course. Highly recommended for people interested in VLSI CAD design.

M
MM
5

Reviewed on May 13, 2020

It was a great course, I learned a lot of new things from it. And the presentation and explanation of concepts by Prof. Rob A. Rutenbar were amazing!!!

D
DS
5

Reviewed on Sep 22, 2019

An awesome course which I can put to great use in my academic life.

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